In the standard gate first high-k/metal gate (HKMG) process the thickness of the silicide in the gate and source/drain regions cannot be controlled separately. As a result, if the proper thickness is targeted in the source/drain regions, the gate may become fully silicided. A fully silicided gate can negatively affect performance of the device, for example, by generating a high long channel threshold voltage (Vt) variation, or affecting gate resistance-capacitance delay. Conversely, a reduction of silicide thickness in the gate will be accompanied by an insufficient silicide thickness in source/drain regions, which likewise can cause poor transistor performance.
A need therefore exists for methodology enabling adjustment of silicide thickness in the gate and source/drain regions independently, and the resulting product.